1. Field of the Invention
The present invention relates to a semiconductor device including a through electrode and a method of manufacturing the same.
2. Description of Related Art
In recent years, in order to achieve larger-scale integration of semiconductor devices, a three-dimensional mounting technique to stack semiconductor devices has been utilized. In order to adapt to such technique, it has been attempted to provide a through electrode in a semiconductor substrate.
As a method of forming a through electrode, proposed is a method described in Japanese Laid-Open Patent Publication No. Sho 63-127550, for example.
In this method, as shown in FIG. 1A, a source electrode 801 and an oxide film 802 are formed on the front surface (the lower surface in FIG. 10A) of a GaAs substrate 800, and mean while, a photoresist film 803 is formed on the rear surface (the upper surface in FIG. 10A) of the GaAs substrate 800.
Next, a through hole extending to the source electrode 801 is formed by use of the photoresist film 803 serving as a mask.
Thereafter, as shown in FIG. 10B, an Au film 805 is formed on the source electrode 801 and the photoresist film 803 with the photoresist mask 803 remaining unremoved.
Furthermore, as shown in FIG. 10C, the Au film 805 is selectively removed, and the photoresist film 803 is removed as well.
Next, as shown in FIG. 1D, Au plating grows only in the through hole by use of an electroless Au plating bath. The through hole is thus filled with an Au layer 806. In this case, it takes approximately three hours for the Au plating to grow enough.
In addition, as another example of forming a through electrode, also proposed is a method described in Japanese Patent Application Laid-open Publication No. 2005-294582.
In this method, as shown in FIG. 11A, an electro deposited insulating film 902 is formed on an opening portion (hole) 901 formed on a silicon substrate 900. Moreover, a seed layer is formed on the electrodeposited insulating film 902.
Next, a portion of the seed layer other than a portion on the area of the hole 901 is removed. Here, as described in paragraph 0084 of Japanese Patent Application Laid-open Publication No. 2005-294582, the seed layer is formed on the entire surface of the inner wall of the hole 901.
Thereafter, as shown in FIG. 11B, electrolytic plating of Ni is performed. Then, Au plating film 903 is provided on the surface of the seed layer. A large diameter plug 904 is thus obtained.
In the method described in Japanese Laid-Open Patent Publication No. Sho 63-127550, however, there is a problem that it requires some time to form a through electrode since the Au film 805 is formed only on the bottom surface of the through hole, and then the Au plating grows from the bottom to the top of the through hole to form the through electrode.
On the other hand, in the method described in Japanese Laid-Open Patent Publication No. 2005-294582, since a seed layer is formed on the entire surface of the inner wall of the hole 901, the plating around the opening of the hole 901 grows faster than the plating inside the hole 901 does when electroless plating is performed. This is because the plating solution is frequently changed around the opening of the hole 901.
For this reason, there is a problem that the opening of the hole 901 is buried with the plating layer, thereby generating a void inside the hole 901.